Senior Staff Engineer Digital Verification (f/m/div)

Part of your life. Part of tomorrow.

We make life easier, safer and greener, with technology that achieves more, consumes less and is accessible to everyone. Microelectronics from Infineon is the key to a better future. Efficient use of energy, environmentally-friendly mobility and security in a connected world we solve some of the most critical challenges that our society faces while taking a conscientious approach to the use of natural resources. 1 Senior Staff Engineer Digital Verification (f/m/div) Job id

HRC1800327

Job familyResearch & DevelopmentDuration of employmentUnbefristetArt des ArbeitsplatzeshybridEinsteigen alsBerufserfahrene*r

#WeAreIn for jobs that impact everyone's life.

What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Staff Engineer Digital Verification on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Your role

Key responsibilities in your new role

* Create and define verification plans for digital or digital mixed signal designs

* Create new and improve existing verification environments in SystemVerilog/UVM

* Write and execute tests for RTL and gate-level

* Debug issues in design and verification environments

* Lead and coordinate other verification engineers in your projects

* Closely cooperate with architects, designers and other verification engineers

* Mentoring of junior colleagues, consultants and students

* Contribute to enhancement of existing methodologies and flows

Your profile

Qualifications and skills to help you succeed

* University degree in Electrical Engineering, Information Technology, Telematics, or a related field with a focus on electronics

* At least 6 years of professional experience in digital verification; experience in technical leadership is highly desirable

* Expert knowledge of SystemVerilog and UVM and solid understanding of SystemVerilog for design

* Strong scripting skills using technologies such as bash, tcsh, Python, TCL or similar

* Knowledge of formal verification and mixed signal verification is an advantage

* Fluent English language skills with German skills as a plus

We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group H (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

Apply to this position online by following the URL and entering the Job ID in our job search.

https://www.infineon.com/jobs Das Mindestentgelt für die Stelle als Senior Staff Engineer Digital Verification (f/m/div) beträgt 4.905,47 EUR brutto pro Monat auf Basis Vollzeitbeschäftigung. Bereitschaft zur Überzahlung.